1. Field of the Invention
The present invention is generally in the field of fabrication of integrated circuit structures. In particular, the invention is in the field of fabrication of dual damascene via structures.
2. Background Art
It is known in the art that there is an ever-present demand for decreasing semiconductor device sizes and geometries. The demand is fueled by the requirement that each unit area of the semiconductor die supply greater computing power and functionality. The requirement to decrease semiconductor device sizes and geometries has resulted, among other things, in a need to reduce width of vias in interconnect structures. Another reason for the need to reduce width of vias is that due to the ever-decreasing space between neighboring interconnect metal lines, wide vias may cause shorts to neighboring interconnect metal lines which are laid out close to the interconnect metal line contacting the via.
Thus, it is generally appreciated in the art that narrow vias are desirable for reasons such as those mentioned above. Despite the desire to reduce the width of vias, there has been no pressing need to reduce the depth of vias to achieve performance improvements. There is no compelling requirement to reduce vertical space or dielectric thickness between two vertically adjacent interconnect metal layers. In fact, reducing dielectric thickness results in an increase in interconnect capacitance which degrades performance of the semiconductor chip. Moreover, as the number of interconnect metal layers increases, it is desirable to use thicker dielectric layers between the higher interconnect metal layers. The reason is that metal line widths for the higher interconnect layers are usually greater than metal line widths for the lower interconnect metal layers. Larger line widths result in larger inter-layer capacitance. As such, thicker dielectric layers are desired in order to decrease, or at least to prevent a potential increase in, the inter-layer capacitance between the higher interconnect metal layers. Thus, as the number of interconnect metal layers have increased, vias have had to be formed through thicker dielectrics existing between the higher interconnect metal layers. However, via widths connecting the higher interconnect metal layers to the lower interconnect metal layers should still be small in order to accommodate the smaller metal line widths of the lower interconnect metal layers.
Since it is desirable to reduce the width of vias while preserving or even increasing their depth, the "aspect ratio" (i.e. the ratio of via depth to via width) has been continually increasing. As aspect ratio of vias increase, it becomes more difficult to properly etch the via hole in the dielectric. The reason is that it becomes more difficult to perform the necessary anisotropic etch required to reach the desired bottom of the via without running into a number of problems. For example, it might be difficult to perform a plasma etch since the plasma might not reach the desired depth of the via. Also, even if the plasma reaches the desired depth, other parts of the semiconductor die undergoing fabrication may be undesirably removed due to the longer than typical exposure to plasma. For example, as the geometry of semiconductor and interconnect structures decreases, thinner photoresist must be used due to limitations in depth of focus in photolithography and the longer than typical exposure to plasma results in exhausting the photoresist. The challenge to etch deep and narrow via holes becomes even more difficult in fabrication of dual damascene interconnect structures. A typical method to fabricate vias in dual damascene interconnect structures requires deposition of both the via dielectric and the trench dielectric. The via hole must then be etched through both the via dielectric and the trench dielectric. As such, a deep hole through both the via dielectric and the trench dielectric must be etched.
U.S. Pat. No. 5,753,967 to Lin discusses fabrication of high aspect ratio vias. Lin discloses a technique for forming a trench and a via in a first dielectric and then reducing the width of the trench and the via by depositing a second dielectric into the trench and the via. According to Lin, the second dielectric would remain in the trench sidewall and it (i.e. the second dielectric remaining in the trench) may be silicon nitride or other dielectric. Dielectrics such as silicon nitride have a high dielectric constant which result in an unwanted increase in line to line capacitance between the interconnect metal lines formed in the trenches.
Moreover, according to Lin, the interconnect metal line width in the trench is reduced due to the second dielectric remaining in the trench. This results in an unwanted increase in the metal line resistance. Although it is possible to start with a wider trench to compensate for the reduction in the interconnect metal width which occurs upon deposition of the second dielectric, starting with wider trenches increases the metal pitch (i.e., the distance between the centers of two neighboring metal lines). This in turn results in a consumption of a larger area of the semiconductor die.
Thus, there is need in the art for fabricating high aspect ratio vias while resolving the shortcomings in the art as explained above.